SSTL_3, V, defined in EIA/JESD ; SSTL_2, V, defined in EIA/ JESDB used in DDR among other things. SSTL_18, V, defined in. STUB SERIES TERMINATED. LOGIC FOR VOLTS (SSTL_2). EIA/JESD SEPTEMBER ELECTRONIC INDUSTRIES ALLIANCE. JEDEC Solid State . SSTL (JESD, JESDB, JESD). • HSTL (JESD). LVTTL and LVCMOS were developed as a direct result of technology scaling. With each reduction in.

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An example of this may be address drivers on a memory board. The third clause specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments. Vx ac indicates the voltage at which differential input signals must be crossing. Making this distinction is important for the design of high gain, differential, receivers that are required.

JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard jexd8 to be used either domestically or internationally.

The dc values are chosen such that the final logic state is unambiguously defined, that is once the receiver input has crossed this value, the receiver will change to and maintain the new logic state. VTT is specified as being equal to 0. Units V mV Notes 1 1 0. With a series resistor of jsed8 The tester may therefore supply signals with a 1.

This is accomplished precisely because drivers and receivers are specified independently of each other. If the driver outputs are sized for this condition, then for all other VDDQ voltage jedd8, the resulting input signal will be larger than the minimum mV. However, the drivers are connected directly onto the bus so there are no stubs present.

The system designer will be able to vary impedance levels, termination resistors and supply voltage and be able to calculate the effect on system voltage margins. An example of ringing is illustrated in the dotted wave-form.


This can be expressed by equation-1 or equation An example of this is shown in figure 6. Clearly it is not the intention to show all possible variations in this standard.

Note however, that all timing specifications are still set relative to the ac input level. AC test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate by analysis, that the device will meet its timing specifications under mesd8 supported voltage conditions.

Days after publication of this standard in Mayit was brought to the attention of the sponsor that there were errors in Table 4. Viso Parameter Input clock signal offset voltage Viso variation Min. However, in the case of VIH Max. JEDEC standards and publications are jesdd8 without regard to whether or not their adoption may involve patents or articles, materials, or processes. One advantage jssd8 this approach is that there is no need for a VTT power supply.

In order to meet the mV minimum requirement for VIN, a uesd8 of 8. NOTE 2 A 1.

Stub Series Terminated Logic

The standard defines a reference voltage VREF which is used at the receivers as well as a 9bb VTT to which termination resistors are connected. Typically the value of VREF is expected to be 0. The driver specification now must guarantee that these values of VIN are obtained in the worst case conditions specified by this standard.

Busses may be terminated by resistors to an external termination voltage. All recipients of this errata are asked to replace page 7 with the corrected page included in this errata.

See also figure 2. External resistors provide this isolation and also reduce the on-chip power dissipation of the drivers. Under these conditions VOH is 1. The specifications 9v quite different from traditional specifications, where minimum values for VOH and maximum values for VOL are set that apply to the entire supply range.


O rgan iz atio ns m ay ob tain perm issio n to rep rod uce a lim ited n um b er o f co pies thro ugh enterin g in to a licen se agreem en t. However a Jeed8 II buffer would dissipate more power due to its larger current drive and thus might require special cooling.

Jssd8 however, that all timing specifications are still set relative to the differential ac input level. The information included in JEDEC standards and 9v represents a sound approach to product jdsd8 and application, principally from the solid state device manufacturer viewpoint.

The Standards, Publications, and Outlines that they generate are accepted throughout the world. F or info rm ationcon tact: JEDEC is the leading developer of standards for the solid-state industry, they have published over documents to date.

Stub Series Terminated Logic – Wikipedia

Units V V Notes 2. If the driver maintains a resistance lower than the Maximum On Resistance, more than the mV will be presented to the receiver. NOTE 4 AC test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate by analysis that the device will jedd8 its timing specifications under all supported voltage conditions. However in order to provide a basis, the driver characteristics will be derived in terms of a typical 50?

The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs. The first clause defines pertinent supply voltage requirements common to jesd88 compliant ICs.

An example is shown in figure 7. The test circuit is assumed to be similar to the circuit shown in figure 5. An example is shown in figure 8. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. While driver characteristics are derived from a 50? This is jes8 in figure uesd8.